In its pure state, silicon is a dull grey crystalline material and a poor conductor of electric current. Yet, with the addition of small quantities of certain impurity atoms, also referred to as electrical dopants, it can be transformed into a plethora of electronic devices, making silicon the foundation of the $350B semiconductor industry.

The preferred method of introducing electrical dopants in the chip fabrication process is to mask off the regions of interest, bombard the silicon with a high energy beam of the required dopant source, and then anneal the wafer; heating it to a high temperature and cooling it in a controlled manner.

Huge advances in lithography (the masking step) have enabled the lateral feature sizes of the doped regions to be scaled to a few nanometers (billionths of a meter), so that billions of transistor devices can be put on a single silicon wafer.

In fact, the advances in the lateral resolution of lithography are now outpacing the ability to control doping in the vertical direction. The various anneals and oxidation steps in most fabrication processes cause the profile of implanted dopants to “smear out” (diffuse), which can in turn impair the performance of the silicon, for example by reducing the current or by increasing the device-to-device variability.

One of the most common steps in most semiconductor processes is an oxidation of the silicon surface. It is well-known that this process injects many imperfections (interstitials) into the silicon. This flood of interstitials speeds up the diffusion of dopants such as boron and phosphorus, so that, like the action of waves on a sandcastle, the original doping profile is significantly broadened.

The dopant broadening under oxidation is illustrated in the experimental results of figure 1.

Atomera has demonstrated that its MST® technology can be used to inhibit the vertical smearing of dopants, with up to an order of magnitude better vertical control than current processes. We believe that this result is highly significant for the design of many silicon devices, and can be used to considerably reduce the variability of various parameters, allowing tighter specifications, reduced power consumption and improved yield. Figure 2 shows how Atomera technology can be used to sculpt the doping profiles, in this case to retain the doping level in the right hand peak. It shows the original dopant (in blue), and the dopant after processing (in red). This ability to manage dopant profiles is very valuable to semiconductor manufacturers because it can positively impact chip performance.

Figure 1 – Boron diffusion, no MST                 Figure 2 – Boron diffusion with MST

Atomera is being supported by Synopsys to facilitate the modeling of MST technology in the industry-leading silicon design software, Sentaurus^TM TCAD. Using this TCAD tool will help technologists and semiconductor engineers quickly determine and evaluate the scale of advantages they can achieve by using MST. As an example, below are simulations of the dopant diffusion experiments illustrated above which closely represent the actual results achieved.

Figure 3 – Boron diffusion, no MST                    Figure 4 – Boron diffusion with MST

Typically, achieving experimental results shown earlier in this article takes several weeks or months of wafer processing and testing. Using TCAD, semiconductor companies will now be able to more fully appreciate what level of improvement MST can deliver in only a matter of hours, making it easier for customers to quickly understand how this ground-breaking technology can transform the semiconductor industry.

Synopsys is highlighting the Atomera technology to many of the world’s TCAD engineers during their October Far East seminar series timed to accompany the new Sentaurus release.

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Startup Atomera has had a rough ride since coming public last year, but its novel technology to improve semiconductors bears watching. By inserting a film of oxygen atoms in chips during manufacturing, the company promises to improve performance and reduce energy consumption of chips without the tremendous cost needed to move parts to the latest and greatest manufacturing process.

Atomera’s “MST” technology claims it can give existing chip-manufacturing nodes as much as a half- or a full-node shrink’s worth of improvement, alleviating much of the cost of actually going to a new node.

The increasing difficulty of making semiconductors, and the soaring cost of manufacturing that results, is prompting new approaches to chip making. Intel (INTC) and others are facing what some believe is the “End of Moore’s Law,” the breakdown in the 50-year-old rule of thumb that transistors on a chip double every 18 months or so, bringing down the cost of chips as performance improves.

The notion of the End of Moore’s Law is debated — Intel refutes it — but it’s prompting lots of new ideas in chips. One approach is new chip designs, such as Alphabet’s (GOOGL) Google’s “Tensor Processing Unit,” a custom chip, something I explored in a recent article for Barron’s print magazine.

Another approach is to do more with what the chip world already has in its manufacturing kit.

I sat down recently with the management of one company doing the latter, called Atomera (ATOM).

Moore’s Law is “no longer a law in terms of the time frame” of improvement of chips, says Scott Bibaud, who took over as chief executive of Atomera in 2015. “In 2012, the cost per transistor for the first time did not go down,” he observes, an ominous sign for the industry.

“In the old days it was pretty clear what you would get from a node shrink, and now it’s no longer clear,” he says.

A node is chip-industry jargon for a change in the critical dimensions of transistors on a chip.

For example, most cutting-edge chips today are made in a 14-nanometer node, with the critical feature of the transistor measuring 14 billionths of a meter. That’s a reduction in size from the prior 20-nanometer node (though different chip makers will have slightly varying measurements.) All chip makers, including Intel and Taiwan Semiconductor Manufacturing (TSM), the largest contract chip maker in the world, serving individual “fabless” chip companies such as Qualcomm (QCOM), spend a considerable amount on R&D to move their parts from one node to another.

Atomera’s principle drive today is to license a set of technologies that will let companies do more with existing chip nodes, thus alleviating the immediate need to move every chip to the next-smallest node.

It’s been a rough ride for Bibaud and company in the stock market in the year since Atomera came public, with the shares dropping over 40% to a recent $4.42. Like some other intriguing tech firms, such as Pixelworks (PXLW), Atomera is a development-stage, pre-revenue company. It is working with four customers at the moment, whose names it cannot disclose, to evaluate the technology, hopefully leading to sales at some point.

Not helping the stock is that it has no coverage on the Street from the sell side.

Participating in the discussion I had was Bibaud, who was previously running the communications and broadcast chip division of Altera, which was bought by Intel; his CFO, Frank Laurencio,, who has a background at various tech companies and in tech investment banking; and CTO Robert Mears, who has authored hundreds of patents and publications, and who has a masters degree in physics from Oxford and a PhD in electronics and computer science from England’s University of Southampton.

It was Mears who originally founded the predecessor company, Nanovis, back in 2001, based on work in “nano-scale engineering.”

The key technology, called “Mears Silicon Technology,” or “MST,” is described by Bibaud as “a film that people put in an existing node that makes it perform significantly better.”

The approach consists of “carefully” placing oxygen atoms in the “channel region” that sits between the source and drain of a transistor, a process that is tricky, because “you can destroy the transistor” if you don’t do it right.

When done right, electrical current is improved in a silicon die, and leakage current is reduced, as depicted in the slide at the top of this post.

The result is to give a chip at any given node either improved performance, or lower power consumption, or some combination of the two, which is why most companies move down to smaller nodes.

That brings immediate benefits in things like the size of a chip. For example, “power management [chips], or anything with relatively high power, requires one to add a lot of circuitry,” says Bibaud. “If you lower the power requirement, you can do away with the oversize-wide transistors,” reducing the size of the device.

A further, bigger result is that chips can stay in older production nodes, rather than moving to the latest and greatest in order to get better performance and efficiency. And that can potentially save chip makers the big up-front expense of having to move to that next node.

Bibaud says his business is in line with trends in the industry of sticking with older technology for longer.

“The cutting edge nodes cost so much that people are talking about how to use legacy nodes,” says Bibaud.

“People are saying 28-nanometer will be useful for many years,” he adds. “And 40-nanometer chips are big in the world of automotive chips and for the Internet of Things.”

“We’ve even heard that the 130-nanometer node has the most new design starts of any node today for things like analog and sensor and power applications.”

Bibaud notes that a contract chip maker like TSM may have a 40-nanometer fab, or factory, say, that’s been running at capacity. Customers using that 40-nano process may be facing the choice of moving chips to 28-nano, but may not want to make the jump  because of the cost of doing so.

DRAM makers, for example, could look to make improvements in their wares using conventional “2-D transistors” rather than bearing the expense of moving to the newer 3-D parts.

Because Atomera’s technology is a way to squeeze more out of existing chip technology, it is not the same as the equipment business dominated by Applied Materials (AMAT) and Lam Research (LRCX), says Bibaud.

“It’s outside the normal capex cycle,” says Bibaud. “And it is in a sense counter-cyclical: when people can’t afford to do major investments, this lets them boost up the performance of their existing equipment.”

In addition to helping with the older nodes, MST is applicable across any “geometry,” or node, says Bibaud, including “mainstream” ones such as 90-nanometer, 65-nanometer, or even 28-nanometer, and ultimately the most cutting-edge nodes as well.

Bibaud and Mears see the technology not only helping with costs, but also making possible some novel classes of devices in the case of cutting-edge nodes.

“This can have a big improvement in DDR [double-data-rate] DRAM for phones,” for instance. “You could produce an entirely new class of mobile DRAM, either making the DDR smaller, while maintaining the power levels, or keep them the same size and lower power consumption.”

During evaluation, potential customers determine what the performance improvement will be with the technology. “We can tell them maybe they will get 10% to 20% improvement, though it varies. It might be that, say, transistors will run 15% faster and with 8% less power draw. There’s a pretty wide range of performance improvements” that can be achieved.

Atomera has shown that there can be improvements of as much as 88% for a given node, “which is phenomenal,” says Bibaud. “Now, not everyone gets that, but probably, it has to be at least 15%” to justify the investment.

Atomera expects to ultimately make revenue off both licenses and royalties. There is a one-time license fee, then Atomera gets paid royalties based on volume of finished wafers shipped, or finished chip shipments in some cases.

The business is comparable to that of Tessera, which gets royalties on chip packaging (owned by Xperi(XPER)), he says, or that of Rambus (RMBS), the memory-chip technology licensor.

The chip makers “are very, very large,” he observes, “and we are a pretty small company, so we can charge a very modest royalty level, and stay lean and bring some very valuable IP because we can scale efficiently.”

But there’s a bit of a wait for actual sales, and Bibaud is not forecasting revenue at this point. With customers in an “evaluation phase,” it’s possible at any time they will decide they are ready to sign a license agreement with Atomera, he says. “We’re waiting for that first big breakthrough on the license business,” he says.

“It’s kind of like a drug development pipeline,” says Bibaud. “We are in the development stage” with the four customers, he says. In addition, the company has a partnership with chip tools maker Synopsys(SNPS), who integrates MST into its simulation modeling software for chip design. “The bulk who are testing are in leading analog chip” areas, he says.

“I don’t know if I can quantify the degree of confidence I have in their signing,” he says, “but they are spending a lot of money in evaluation, it’s quite expensive,” suggesting that they wouldn’t be doing so only to end up walking away.

Atomera, with just under 20 employees at the moment, is currently staffing up because “we’re bringing in a lot of new customers” in the evaluation stage.

“Our spending is not on staff but on expensive lease facilities to run this testing,” says Bibaud. He says Atomera is “very well capitalized,” with “almost three years of burn left” in terms of cash on hand. Cash and equivalents at the end of the June quarter was just under $22 million, according to the company’s 10-Q filing.

“So hopefully, we will be at revenue and cash flow before we have to raise anything further” in the capital markets, he says.

Mind you, the company filed a $30 million mixed securities shelf offering earlier this month, to allow it to sell shares if it chooses to at some point. Bibaud told analysts this month that the filing is “a tool used by virtually all public companies to efficiently position themselves for potential future fundraising.”

“As you can see from our financials, we are very well-positioned with over two years of cash in the bank and therefore have no near term plans to raise capital,” Bibaud said.

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Welcome to Atomera’s new Blog. We hope to use this forum to provide insight into our company and our connection to some of the biggest developments in the semiconductor industry. To kick it off, we will explore in more detail how Mears Silicon Technology, or MST, fits the with the larger trend of the slowdown in Moore’s law.

Moore’s Law

In 1965, Gordon Moore observed that the number of transistors per square inch in an integrated circuit doubles approximately every two years.

Consumers interpret that statement in many ways: that computing power will double every few years, that the cost of the same electronic capability will continuously decline over time, and that power consumption will likewise considerably decrease every two years. For the most part, these statements have held true over the last 50 years, but this relentless march to higher performance and lower cost was not due solely to putting more transistors on the same piece of silicon. Advanced material innovations, which were introduced alongside smaller line widths, also provided enormous value. Atomera’s MST technology is one of the newest material innovations that will continue the advancement of Moore’s Law.

Advanced materials have been instrumental in the history of semiconductors including: strained silicon, copper interconnects, high-k dielectrics and many others. For example, in 1990 Judy Hoyt and Eugene Fitzgerald introduced the concept of straining silicon to stimulate better performance. The technology was developed in the 90’s and went into production by many suppliers between around 2003-2007. Mark Bohr wrote a very interesting article on one of these: The Invention of Uniaxial Strained Silicon Transistors at Intel.   https://www.intel.com/pressroom/kits/advancedtech/doodle/ref_strain/strain.htm

This article gives great insight into both the challenge and opportunity facing Atomera. He says: “Solving all the integration, yield and manufacturing issues with a new material… was quite a challenge, but is something that Intel…excels at.” He then talks about how strained silicon was rapidly adopted by the rest of the industry.

Why today is different

Today the industry is experiencing much greater difficulties continuing the historical rate of extending Moore’s Law. Major semiconductor companies continue to push their flagship chips into expensive, leading-edge FinFET technologies like 7nm. But, because these nodes are so expensive, they aren’t a good choice for many new chip designs. Engineers are looking for ways to improve performance without having to take on the cost burden of the latest new node.

For that reason, more so than ever before in the industry, manufacturers are looking for ways to squeeze more out of existing fabs and processes. That is where MST provides a great solution. MST is an additive technology that can provide benefits on top of other geometric and material improvements. Almost any fab/process can get improvements using MST. And it is more relevant today than it has ever been. In the past, an engineer trying to find higher performance would simply redesign in the newest process node which was being released every two years. Today, only the largest and highest performance chips can justify a redesign into leading-edge process nodes, and those nodes are taking far longer to be released. Designers must be more creative. And MST gives them a new tool to attack the problem.